The present application relates to semiconductor device manufacturing, and more particularly, to a method of forming a semiconductor structure containing different channel materials within different device regions of a semiconductor structure.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
One challenge facing continued size reduction is developing high performance MOSFET devices with smaller gate lengths. One approach to increase performance with smaller gate lengths is to increase the carrier mobility, i.e., electron and/or hole, in the channel. Although it is possible to obtain higher carrier mobilities with strained silicon, much higher mobilities can be achieved by using a different semiconductor material in the channel other than silicon. For example, hole mobility in silicon germanium (SiGe) is known to be much higher than in silicon.
In certain technology node device requirements, it may be necessary to provide a substrate that contains different channel materials in which n-field effect transistor (nFET) and p-field effect transistor (FET) devices can be formed. For example, enhanced device performance can be obtained by forming an nFET device on a silicon channel material, while forming a pFET device on a SiGe channel material.